Eusebio Rodrigo, José Rebollo, Xavier Jordà, José Camps, Llorenç Latorre and Miquel Vellvehi.

Electronics 2026, 15, 1201

Single-Event Burnout (SEB) is one of the most critical failure mechanisms in silicon power
MOSFETs operating in radiation environments, particularly under heavy-ion irradiation,
and often limits device operation through excessive voltage derating. In this work, SEB
robustness of a silicon VDMOS power device is investigated using detailed electro-thermal
transient simulations. The study evaluates two complementary device-level modifications:
the introduction of a buffer layer between the epitaxial layer and the substrate, which has
been reported in the past, and a new approach considering the incorporation of a novel
highly doped boron BOX implant within the P-body region. Heavy-ion impacts are simulated
using a physically based model implemented in SENTAURUS TCAD, accounting
for ion energy deposition, impact position, and thermal effects. The results show that
the buffer layer increases the second breakdown voltage and can suppress high-current
operating points, while the BOX implant raises the parasitic BJT activation threshold by
reducing the P-body resistance. When combined, both modifications lead to a significant
reduction in the peak temperature reached during after-impact transients, without introducing
measurable degradation of static electrical characteristics. These results demonstrate
that combining buffer layer engineering with localized P-body resistance reduction is an
effective strategy to improve SEB robustness in silicon VDMOS power devices without
relying on excessive derating.

Link DOI: 10.3390/electronics15061201